Uni Connect Pte Ltd

Implement and debug FPGA designs on AMD FPGA based prototyping platforms using Xilinx Vivado and ISE tools.Implement and debug FPGA designs on a Stratix10 development board using Intel Quartus prime Pro. Support a regression testsuite consisting of systemlevel test cases to validate u المزيد...

Key Responsibilities: Static Timing Analysis (STA): Perform comprehensive timing analysis using tools like NanoTime for advanced process nodes (2nm/3nm). Develop and validate timing constraints for highperformance designs. Identify and resolve timing bottlenecks to ensure المزيد...

Key Responsibilities: Design and Development: Architect and develop highspeed SerDes circuits including PLLs CDRs equalizers and transmit/receive paths for advanced process nodes (2nm/3nm). Optimize analog and mixedsignal circuits to meet performance power area and reliabilit المزيد...

Key responsibilities: ATE Test Program Design and Development for new products (Production and Characterization Test) Design/Develop Final Test Loadboard and Wafersort Probecard Perform Characterization Testing prepare test specifications المزيد...

ResponsibilitiesOwn and be responsible for pretape out quality for digital SOC modules on the MCUExplore architecture and develop microarchitecture.RTL development for IPs and SOCs using Verilog3rd party IP identification selection and integrationCollaboration with verification and FP المزيد...

Key ResponsibilitiesSoftware DevelopmentDesign Develop and Maintain device drivers for Windows Operating SystemsUndertake WHQL testing and certification of drivers and device frameworksDesign Develop and Maintain user libraries and DLLsParticipate in all phases of SDLC and prepare cor المزيد...

Job Responsibilities: Perform detailed STA on digital designs used in networking and audio solutions at various stages of the IC design flow (prelayout postlayout).Identify analyze and resolve timing violations in critical paths ensuring low latency and high throughput for networking المزيد...

ResponsibilitiesYou will be responsible for verifying digital and mixedsignal designs including systemsonchip with multiple CPUs digital signal processors security hardware and other logic for IoT applications.Specific responsibilities include:The right candidate will be a selfstarter المزيد...

ResponsibilitiesResponsible for high quality ontime tapeouts with good influencing driving collaboration skills.Drive Interlock meeting between functions. Collaborate closely with Arch SW validation and product/application teams. Attract and retain a world class team of RTL and DV eng المزيد...

ResponsibilitiesOwn and be responsible for pretape out quality for digital SOC modules on the MCUExplore architecture and develop microarchitecture.RTL development for IPs and SOCs using Verilog3rd party IP identification selection and integrationCollaboration with verification and FP المزيد...

ResponsibilitiesYou will be responsible for verifying digital and mixedsignal designs including systemsonchip with multiple CPUs digital signal processors security hardware and other logic for IoT applications.Specific responsibilities include:The right candidate will be a selfstarter المزيد...