drjobs Lead engineer-Design verification

Lead engineer-Design verification

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1 Vacancy
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Job Location drjobs

Singapore - Singapore

Monthly Salary drjobs

Not Disclosed

drjobs

Salary Not Disclosed

Vacancy

1 Vacancy

Job Description

Responsibilities

You will be responsible for verifying digital and mixedsignal designs including systemsonchip with multiple CPUs digital signal processors security hardware and other logic for IoT applications.

Specific responsibilities include:

  • The right candidate will be a selfstarter who assumes full ownership of DV tasks and delivers highquality results.
  • Develop test plans at block subsystem and chip level.
  • Execute SoCbased verification at fullchip.
  • Write Cbased lib packages and tests.
  • Architect and implement scalable and reusable test benches using SystemVerilog and UVM.
  • Develop comprehensive test cases stimulus generation and checkers to achieve high coverage.
  • Automating the test environment for randomized testing and scoreboarding.
  • Utilize advanced debugging techniques to identify and resolve design and verification issues.
  • Perform rootcause analysis and work with design teams to fix identified issues
  • Define and track functional and code coverage metrics to ensure thorough verification.
  • Ensure that verification quality meets or exceeds industry standards and project requirements.
  • Edgebased AI inference is preferred.


Requirements

Requirements

Requirements

What you need to have to be successful

  • BSEE /MSEE 812 years Degree of experience in block subsystem and fullchip verification
  • Should have delivered multiple chips functioning to Specification.
  • Identify and manage verification deliverables milestones and schedules.
  • Proactively identify potential verification risks and develop mitigation strategies.
  • Collaborate with design architecture and software teams to understand and verify design intent.
  • Communicate verification progress issues and results to stakeholders and management.
  • Strong in understanding multiple architectures integrating 3rd party IPs/VIPs and working with mixedsignal designs with lowpower design and verification challenges
  • Strong understanding/exposure to Design Verification for lowpower batteryoperated designs is highly desired.
  • Cbased verification in an SoC environment is required
  • Experience with ARM processorbased designs and lowpower design techniques is a plus.
  • Languages: SystemVerilog (UVM) Verilog C/C Python Perl or Makefile
  • Technologies: ARM M/RISCV (Preferred) AMBA AXI/AHB/APS DMA Flow Control Serial Devices Qo5
  • Preferred technologies: MIPI(CSI/DSI) Crypto OTP DSP LowPower


Employment Type

Full Time

Company Industry

About Company

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