Perform detailed STA on digital designs used in networking and audio solutions at various stages of the IC design flow (prelayout postlayout).
Identify analyze and resolve timing violations in critical paths ensuring low latency and high throughput for networking and audio processing applications.
Conduct multimode multicorner (MMMC) analysis to ensure timing closure under different operating conditions including powersaving modes.
Develop validate and optimize timing constraints tailored for highspeed networking interfaces and highfidelity audio processing circuits.
Define and validate clock definitions I/O constraints multicycle paths and false paths ensuring robust performance in realworld applications.
Work closely with the Physical Design team to address timing issues suggest optimizations and support clock distribution for complex networking and audio processing circuits.
Perform final timing analysis and signoff ensuring that our ICs meet stringent timing area and power requirements for networking and audio applications.
Work with postsilicon validation teams to correlate timing models with actual silicon measurements ensuring that our networking and audio solutions perform as expected in the field.
Requirements
Requirements:
Bachelor s or Master s degree in Electrical Engineering Computer Engineering or a related field.
6 years of experience in STA for digital ICs preferably in the networking or audio domain.
Strong understanding of digital design principles timing concepts and semiconductor physics.
Experience with timing analysis for designs at 28nm and below with a focus on highspeed data and signal processing.
Proficiency in STA tools such as Synopsys PrimeTime Cadence Tempus or similar.
Solid understanding of CMOS technology standard cell libraries and PVT variations with a focus on highperformance networking and audio applications.
Strong scripting skills (e.g. TCL Perl Python) for automation of STA processes.
Ability to work in a collaborative environment with excellent communication and problemsolving skills.
Experience with timing analysis for highspeed networking interfaces (e.g. Ethernet WiFi) or audio processing circuits (e.g. DACs ADCs).
Familiarity with lowpower design techniques and their impact on timing.
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