AGE Groups Jobs in Vietnam

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Define DFT strategy architecture and provide technical guideline for DFT design & verificationPerform DFT design and verification (MBIST SCAN LBIST...)DFT mode SDC (timing constraint) develop & analysis.Analyze & improve test coverage test time reduce area/timing/routing c More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Our team is performing design for system IP (such as CPG SYSC) as the below steps: Make DRBFM target specification implementation specification. Understand clock/reset/power structure for whole SoC to generate/coding full or a part of IP. Understand to create timing constraint for IP More...

Define DFT strategy architecture and provide technical guideline for DFT design & verificationPerform DFT design and verification (MBIST SCAN LBIST...)DFT mode SDC (timing constraint) develop & analysis.Analyze & improve test coverage test time reduce area/timing/routing c More...

Your New Roles:Application monitoring to ensure stable and optimal performance always.Have ability to understand and reasonably resolve basic and complex technical problems.Have ability to work under pressure prioritize and manage multiple tasks.Good Teamplayer with strong Interperson More...

Define DFT strategy architecture and provide technical guideline for DFT design & verificationPerform DFT design and verification (MBIST SCAN LBIST...)DFT mode SDC (timing constraint) develop & analysis.Analyze & improve test coverage test time reduce area/timing/routing c More...

Define DFT strategy architecture and provide technical guideline for DFT design & verificationPerform DFT design and verification (MBIST SCAN LBIST...)DFT mode SDC (timing constraint) develop & analysis.Analyze & improve test coverage test time reduce area/timing/routing c More...

Define DFT strategy architecture and provide technical guideline for DFT design & verificationPerform DFT design and verification (MBIST SCAN LBIST...)DFT mode SDC (timing constraint) develop & analysis.Analyze & improve test coverage test time reduce area/timing/routing c More...

Our team is performing design for system IP (such as CPG SYSC) as the below steps: Make DRBFM target specification implementation specification. Understand clock/reset/power structure for whole SoC to generate/coding full or a part of IP. Understand to create timing constraint for IP More...

Our team is performing design for system IP (such as CPG SYSC) as the below steps: Make DRBFM target specification implementation specification. Understand clock/reset/power structure for whole SoC to generate/coding full or a part of IP. Understand to create timing constraint for IP More...