Design for Testability DFT Engineer
Design for Testability DFT Engineer
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Job Description
As a DFT Engineer you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design verification and physical design teams
Responsibilities:
Develop and implement DFT architectures and strategies for complex SoC designs.
Insert and verify DFT features such as scan chains BuiltIn SelfTest (BIST) for memory and logic and boundary scan (IEEE 1149.1/1149.6).
Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage.
Collaborate with RTL designers to ensure seamless integration of DFT features into the design.
Debug and resolve testrelated issues in simulation silicon validation and production.
Work closely with the physical design team to implement scan and clock constraints for timing closure.
Optimize test time power and cost without compromising coverage and quality.
Participate in silicon bringup and postsilicon validation activities.
Generate and maintain DFT documentation including test plans methodologies and results.
Requirements:
Bachelors or Masters degree in Electrical Engineering Computer Engineering or related field.
4 to 10 years of experience in DFT for VLSI designs.
Strong knowledge of DFT methodologies including ATPG/MBIST/Scan Insertion
Verilog/ System Verilog and scripting languages (Python TCL Perl).
Solid understanding of STA concepts and constraints related to DFT.
Experience in debugging silicon and ATE test patterns.
Excellent problemsolving skills and ability to work in a collaborative environment.
Familiarity with fault diagnosis and yield improvement methodologies.
Exposure to advanced nodes (7nm 5nm or below) and FinFET technologies.
Knowledge of machine learning or AI techniques for test optimization.
Employment Type
Full Time
