Overview
The DFT Engineer plays a critical role in ensuring the testability quality and manufacturability of integrated circuits (ICs). They are responsible for implementing design for test (DFT) techniques to enable effective testing and diagnosis of ICs contributing to the overall success of the product development process.
Role: DFT Engineer
Experience: 7 Years & 10 years
Location: Bangalore
Required Skills:
Handson experience in Scan Insertion ATPG GLS debug MBIST pattern generation and validation. A basic understanding of DFT IPs like OCC EDT SSN MBIST controllers IJTAG IEEE 1600 standard and Boundary scan.
Should be able to handle tasks independently. Should have good debugging skills.
Working knowledge of TCL is an addon.
Experience with tessent DFT a preference.
Required qualifications
- Bachelors or higher degree in Electrical Engineering Computer Engineering or a related field.
- Proven experience in DFT ATPG and scan insertion for complex digital designs.
- Strong understanding of DFT architectures and methodologies for scan ATPG and MBIST.
- Familiarity with JTAG boundary scan and IEEE 1500 standards.
- Proficiency in RTL simulation tools and gatelevel simulations for DFT analysis.
- Handson experience with DFT tools such as TetraMAX DFT Compiler and Mentor Tessent.
- Knowledge of DFTrelated EDA tools and scripting languages (e.g. TCL Python).
- Experience in silicon bringup test debug and failure analysis.
- Strong problemsolving skills and ability to work in a dynamic fastpaced environment.
- Effective communication and collaboration skills for crossfunctional teamwork.
- Ability to multitask prioritize and drive results in a deadlinedriven environment.
- Detailoriented approach with a focus on quality and continuous improvement.
- Ability to adapt to new DFT techniques and methodologies as per project requirements.
- Understanding of DFT for lowpower designs and test compression techniques.
- Previous experience in mentoring or leading DFTrelated projects is a plus.
atpg,eda tools,silicon bring-up,automatic test pattern generation (atpg),dft,ssn,test compression techniques,communication,prioritize,multitask,test debug,ijtag,drive results,rtl simulation tools,mentor tessent,low-power designs,tcl,mbist pattern generation,problem-solving,mbist controllers,tessent dft,scan insertion,collaboration,dft compiler,failure analysis,tetramax,ieee 1600 standard,dft ips,occ,edt,boundary scan,python,leading projects,gate-level simulations,scripting languages,debugging,gls debug,mentoring,adapt to new dft techniques