DFT Lead
DFT Lead
Posted on :
28-09-2024
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Job Description
Position Name DFT Lead
Type of hiring 12 Months
W2 or C2C
Location Santa Clara CA (Onsite)
Job Description:
- Knowledge of Testability techniques and features (SSN Compressed Scan BuiltinSelfTest Boundary Scan) covering digital logic domain embedded memories
- Well versed in JTAG / 1500 / 1687 networks. BSDL ICL and PDL knowledge preferable
- Expertise in DFT RTL insertion ATPG coverage analysis and zerodelay / SDFbased pattern simulations required. Experience with Mentor DFT tools (Tessent Shell) required
- Good knowledge of Verilog logic design
- Working knowledge of TCL python (or another scripting language like Perl)
Thanks & Regards
Nikhil Errapati
Resource specialist
Email Id:
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Employment Type
Full Time
Key Skills
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