Sr Digital Verification Engineer
Sr Digital Verification Engineer
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Salary Not Disclosed
1 Vacancy
Job Description
Job Responsibilities:
- Collaborate with architects hardware engineers and firmware engineers to understand the new features to be verified.
- Build test plan documentation accounting for interactions with other features the hardware the firmware and the software driver use cases.
- Estimate the time required to write the new feature tests and any required changes to the test environment.
- Build the directed and random verification tests.
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
- Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements.
Job Requirements:
- Proficient in IP/SoC level ASIC verification.
- Proficient in debugging firmware and RTL code using simulation tools.
- Proficient in using UVM testbenches and working in Linux and Windows environments.
- Strong background with UVM Verilog System Verilog C and C.
- USB UFS Ethernet PCIE AXI knowledge is a plus.
- Developing UVM based verification frameworks and testbenches processes and flows.
- Automating workflows in a distributed compute environment.
- Exposure to power aware simulations is a plus.
- Good understanding and handson experience in the UVM concepts and System Verilog language. (SVA UVM scoreboard)
- Good working knowledge of System C and TLM with some related experience.
- Scripting language experience: Perl Ruby Make file shell preferred.
- Exposure to leadership or mentorship is an asset.
- Min 5 15yrs of digital IP verification with SV/UVM/formal verification or new methodology of the industry.
- Must be able to work independently on various DV task and providing technical guidance to DV team.
- Proficiency in Bahasa Melayu English and Mandarin because will have to communicate with China customer.
Employment Type
Full Time
