Principal Engineer ASIC Development Engineering CAD PDK PCELL LVS 7Years
Principal Engineer ASIC Development Engineering CAD PDK PCELL LVS 7Years
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Job Description
- You are responsible for the further development of concepts and methods for the EDA design environments with focus on analog / mixed signal ASIC design in advanced nodes.
- Solid understanding of PDKs effectively manage PDK libraries collaterals and drive migration of design environments for incremental releases.
- Development of Calibre Physical Verification decks for cmos PLANAR and FINFET technologies including DRC LVS PERC FILL LPE and shape generation decks and scripts.
- Layout Automation and Utilities development in Cadence SKILL/SKILL.
- Development and validation of PV tools and flows like parasitic extraction EMIR drop and substrate noise analysis.
- Responsibilities will include testing validation customer support and new tool/methods evaluations development of methods and procedures for quality improvement automation of deck/techFiles generation and validation.
- Experience with Cadence custom IC Virtuoso platform to create layout test structures to validate verification rules and to troubleshoot errors.
- Experience with physical verification tools for DRC LVS and parasitic extraction Calibre starRC ICV etc is plus.
- Working knowledge of revision control software (Git Perforce Subversion Synchronicity etc)
- Collaboration with the IT team to fulfil advanced nodes specific requests (Linux ExceedonDemand Grid VMWareESX Storagesystem etc.).
- Ensuring the operation and support within the CAD / ITteam for all ASIC designers worldwide.
- Managing the quality and ISO26262 requirements for the EDA tools both for inhouse developments and vendor products.
Qualifications :
- Education: University degree (Master/PhD) in electrical engineering or a comparable subject
- Personality and working practice: communicative problemsolving mindset responsible initiative flexible and target oriented. Comfortable in working in a fast paced dynamic environment with changing priorities.
- Experience and Knowledge: Minimum 10 years of development experience of Mixed Signal CAD design Flows from Front to Back expert knowledge and experience of stateoftheart design tools (EDAvendors e.g. Cadence Synopsys Mentor) and Softwaredevelopmentmethodologies and tools (Linux script and programminglanguages as well as Cadence Skill) thorough understanding of Custom Analog development flow design tools and Software / Hardware environment
- Qualifications: ability to identify and analyse tasks efficiently within the scope of your work and to develop pragmatic applicationspecific solutions; pronounced ability to communicate relevant experience in the methodology of problem solving as well as in the cooperation and leadership of international and crossfunctional teams
- Technical Skills: Cadence SKILL Calibre SVRF/TVF Python Shell Scripting.
- Languages: fluent in English and German written and spoken
Additional Information :
Western Digital thrives on the power and potential of diversity. As a global company we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees our company our customers and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging respect and contribution.
Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at to advise us of your accommodation request. In your email please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.
Remote Work :
No
Employment Type :
Fulltime
Employment Type
Full-time
