Design Verification Engineer
Design Verification Engineer
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Salary Not Disclosed
1 Vacancy
Job Description
- Develop and execute comprehensive verification plans for complex designs.
- Create detailed test cases based on specification documents.
- Utilize simulation tools to validate designs at various levels of abstraction.
- Perform functional verification to ensure designs meet specifications.
- Conduct code reviews and assist in peer verification processes.
- Generate coverage metrics to assess verification efficiency.
- Debug and troubleshoot design issues using advanced debugging techniques.
- Collaborate with hardware and software teams to improve overall design quality.
- Implement verification methodologies such as UVM or OVM.
- Participate in design reviews to provide input on verification aspects.
- Maintain accurate documentation of verification processes and outcomes.
- Track and resolve identified design and verification issues.
- Conduct regression testing to ensure new changes do not affect existing functionality.
- Stay updated on industry trends and emerging verification tools.
- Mentor junior team members in best practices for design verification.
- Bachelors degree in Electrical Engineering Computer Engineering or related field.
- Minimum of 5 years of experience in design verification engineering.
- Proficiency in SystemVerilog and/or VHDL.
- Handson experience with simulation and verification tools (e.g. Synopsys Cadence).
- Strong understanding of digital design principles and methodologies.
- Experience with verification methodologies such as UVM or OVM.
- Knowledge of scripting languages (e.g. Perl Python Tcl).
- Familiarity with ASIC and FPGA design processes.
- Ability to analyze complex systems and identify potential design flaws.
- Excellent problemsolving skills with a focus on root cause analysis.
- Strong communication skills both verbal and written.
- Ability to work effectively in a teamoriented environment.
- Experience in a fastpaced hightech development environment.
- Attention to detail and commitment to delivering highquality results.
- Prior experience with project management tools is a plus.
ovm,communication skills,simulation tools,cadence,digital design principles,systemverilog,verification methodologies,vhdl,perl,tcl,uvm,python,abstraction
Employment Type
Full Time
Company Industry
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