3 to 10 years of strong experience in digital frontend design (RTL design) for ASICs
Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains
Familiar with UPF and power domain crossing
Experience in Synthesis Logical Equivalence checks RTL and Netlist CLP
Familiarity with various bus protocols like AHB AXI SPMI I2C SPI
Experience in low power design methodology and clock domain crossing designs
Experience in Spyglass Lint/CDC checks and waiver creation
Experience in formal verification with Cadence LEC
Understanding of full RTL to GDS flow to interact with DFT and PD teams
Expertise in Perl/TCL/Python language
Experienced in database management flows with Clearcase/Clearquest.
Expertise in postSi debug is a plus
upf,spmi,tcl,cadence lec,ahb,verilog,spyglass lint/cdc checks,spi,post-si debug,python,rtl and netlist clp,systemverilog,clearquest,axi,clearcase,design,perl,i2c,synthesis,logical equivalence checks,vhdl,low power design methodology,rtl design,bus,clock domain crossing