Design Verification Engineer
Design Verification Engineer
Employer Active
Job Alert
You will be updated with latest job alerts via email
Share
Job Alert
You will be updated with latest job alerts via email
INR INR 6000000 - 7000000
1 Vacancy
Job Description
- Design and implement scalable configurable and reusable verification environments using SystemVerilog and UVM.
- Develop SystemVerilog and/or SystemC models for simulation.
- Create and maintain UVM testbenches including test plans test cases and coverage models.
- Apply constrainedrandom verification methodologies to achieve high functional coverage.
- Analyze simulation results and debug design issues.
- Collaborate with design engineers to improve design quality and testability.
- Stay uptodate with the latest verification methodologies and tools.
- Strong proficiency in SystemVerilog and UVM.
- Experience with digital design and verification methodologies.
- Experience with industrystandard verification tools (e.g. Synopsys VCS Cadence Xcelium).
- Strong problemsolving and analytical skills.
- Excellent communication and teamwork skills.
design,communication skills,systemverilog,uvm,systemc,constrained-random verification methodologies,teamwork skills,verification methodologies,digital design,problem-solving,analytical skills,digital designs,digital
Employment Type
Full Time
Company Industry
Key Skills
- Arabic Speaking
- Logistics Operations
- Lecturing
- Community Support
- Gynaecology & Obstetrics
- AC Maintenance
