Post Silicon Validation Engineer
Post Silicon Validation Engineer
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1 Vacancy
Job Description
7 years of experience in bringing up and debug of high speed and highpower SoCs
7 years of experience in silicon validation planning and leading a project from presilicon planning bringup full SoC validation and characterization to providing validation signoff before HVM
Comprehensive knowledge of Embedded software programming
Proficient in programming languages such as C C Python TCL and Shell scripts
Strong protocol knowledge in I2/I3C SPI UART JTAG and PCIe
Strong understanding of FPGA programming
Proficient in HighSpeed SerDes testing
Proficient in TCP IP UDP IPv4 IPv6 addressing Ethernet DHCP and DNS
Handson experience with highspeed oscilloscopes and debugging embedded systems using logical analyzers
Basic understanding of how LLMs work
Some experience with DFT (Design For Test)
Experience in automation framework development using Python or any other language
Good knowledge of ASIC design flow and silicon FW development process
Flexible to adapt to a very dynamic environment and always carrying forward key improvements
Responsibilities & outcomes:
Responsible for developing an E2E system validation test plan for the SoC including characterization
Collaborate with the SW teams to develop a complete suite of tests that enable maximum systemlevel coverage for validation and characterization
Collaborate with the HW teams to develop the optimum solution for test validation and characterization
Responsible for understanding the SoC design to collaboratively work with crossfunctional teams to create modify edit tests and suggest coverage improvements
Responsible for supporting correlation between the system and other key platforms to enable a robust production plan
Employment Type
Full Time
