High-Speed Interface PHY IP Digital Design Engineer
High-Speed Interface PHY IP Digital Design Engineer
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Job Description
- Responsibilities
- FrontEnd implementation of SERDES high speed Interface PHY designs
- RTL development and its validation for linting clockdomain crossing conformal low power and DFT rules.
- Work with functional verification team on testplan development and debug.
- Develop timing constraints deliver synthesized netlist to physical design team and provide constraints support for PD STA.
- UPF writing power aware equivalence checks and low power checks.
- DFT insertion and ATPG analysis for optimal SAF TDF coverage.
- Provide support to SoC integration and chip level pre/postsilicon debug.
Skills & Experience
- MTech/BTech in EE/CS with hardware engineering experience of 8 years.
- Experience in microarchitecture development RTL design frontend flows (Lint CDC lowpower checks etc.) synthesis/DFT/FV/STA.
- Experience with highspeed interface design and good understanding of Industry standard protocols like USB/PCIe/MIPI etc. is desirable.
- Experience with postsilicon bringup and debug is a plus.
- Able to work with teams across the globe and possess good communication skills.
Minimum Qualifications:
Bachelors degree in Computer Science Electrical/Electronics Engineering Engineering or related field and 4 years of Hardware Engineering or related work experience.OR
Masters degree in Computer Science Electrical/Electronics Engineering Engineering or related field and 3 years of Hardware Engineering or related work experience.
OR
PhD in Computer Science Electrical/Electronics Engineering Engineering or related field and 2 years of Hardware Engineering or related work experience.
We are 26 years old company catering to top notch companies catering to Semicon Industries Telecom and System Software. We are operating out of Delhi Bengaluru and Hyderabad.
Employment Type
Full Time
