Digital ASIC Design Engineer 5G Infrastructure
Job Description:
Join our clients Digital ASIC Design Team to shape the future of mobile network infrastructure products powering nextgeneration 5G connectivity. In this role you will specialize in backend ASIC design and static timing ysis (STA) while thriving in an Agile work environment.
While the client is based in Sweden this role is fully Remote
Responsibilities:
- Lead synthesis timing/area/power optimization and ensure timing signoff for lowpower designs.
- Develop timing constraints execute place and route perform equivalence checking and oversee physical implementation.
- Collaborate with crossfunctional teams to foster continuous improvement and knowledge exchange.
Requirements:
- Bachelors or Masters degree in Electrical Engineering Computer Science or a related field.
- Minimum of 5 years of experience in backend ASIC design.
- Proficiency in EDA tools static timing ysis and timing signoff processes.
- Expertise in lowpower design odologies UPF and hardware description languages (VHDL/System Verilog) along with scripting languages (Python Perl TCL).
- Familiarity with Synopsys tools (Design Compiler FusionCompiler PrimeTime).
- Experience with UNIX/Linux environments and version control systems (e.g. Clear Case Git).
- Strong communication ss in English and a qualityfocused approach to work.
Preferred Qualifications:
- Knowledge of multicore CPU architectures mobile communication standards and telecommunications.
- Experience with Synopsys Spygl Design Compiler and Formality.
Opportunities:
- Engage in innovative backend design projects at the forefront of technology.
- Enhance your professional ss in a supportive and collaborative environment.