Design Verification Engineer
Design Verification Engineer
Employer Active
Job Alert
You will be updated with latest job alerts via email
Share
Job Alert
You will be updated with latest job alerts via email
Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
Greetings from Maneva!
Job Description
Job Title Design Verification Engineer
Location Bangalore
Experience 5 10 Years
Notice Immediate to 15 Joiner
Requirements:
Understanding the business requirements and functional specifications of the IPs
o Creating Verification Environment Architecture document.
o Reviewing and Revising: working towards meeting agreed upon acceptance criteria.
o Developing code in System Verilog UVM (Universal Verification Methodology) C for Unit Subsystem and SOC level verification.
o Performing RTL simulations using Synopsys and Cadence simulators.
o Debugging and resolving problems found by simulations.
o Performance test plan development and maintenance.
o Development of transactors monitors and models for performance verification.
o Implement performance verification flow including monitoring synchronization reporting and selfchecking mechanisms.
o Provide full report of performance metrics and bottlenecks.
o Tracking tickets and code releases using Bug Tracking tool and GIT.
o Performing UPF (Unified Power Format) based Power Aware simulations.
o Coding of Assertion and Functional Coverage bins in SVA (System Verilog Assertions).
o Code & Functional Coverage Closure.
o Performing Gate Level simulations.
o Preparing and conducting reviews of Verification Signoff documents to ensure SOC tapeout quality.
.
If you are excited to grab this opportunity please apply directly or share your CV at and
Employment Type
Full Time
