Design Verification
Design Verification
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Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
Requirements
Requires BSc/MSc or PhD in electrical and electronic or Computer engineering Requires 5 years or more of experience in building UVM/OVM/VMM equivalent test suite Requires strong understanding of state of the art verification techniques including assertion and metric-driven verification methodology, UVM-based Very competent in System Verilog, C++ , C , System C and/or Verilog Experience in writing of CPF/UPF to enable multiple power domain verification Strong experience in working in Synopsys VCS or Cadence IES, and other formal verification tools Verification experience and working knowledge of ARM based CPU Core , SPI, I2C, UART, I2C, USB, PCIe , and/or any other wired protocol with transceivers are strong added advantages Capable of leading, review and guiding younger verification engineers in their daily verification tasks Able to work in a team with a strong drive to excel Able to work independently on a given assignment and work hard to finish on time Good written and communication skills
Employment Type
Full Time
