Design Verification
Design Verification
Posted on :
10-09-2024
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1 Vacancy
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Monthly Salary
Not Disclosed
Salary Not Disclosed
Vacancy
1 Vacancy
Posted on :
10-09-2024
Job Description
To develop UVMbased test suite and simulation environment for the verification of standalone IP level and SoC ARMbased system connected with many peripheral digital IPs and Analog IPs.
Capable of designing and building Verification IP from standard industrial specification
To implement test cases from product and standard industrial specification to ensure SoC achieve highest possible coverage using both constraintrandomized and directed test.
To develop test environment and create test cases with UPF inputs for verification of IPs/SoC level in a multiple power domains SoC to ensure they meet all functional features in their respective power domain.
To document compile and correlate all test cases to meet all features in Functional Requirement specification
To simulate and debug GatelevelNetlist for all corners from backend team Post layout netlist for all corners to close timing before tapeout.
Capable of debug and working with IP designer to identify failures and also improve on functional and Code coverage.
Requirements
Requires BSc/MSc or PhD in electrical and electronic or Computer engineering
Requires 5 years or more of experience in building UVM/OVM/VMM equivalent test suite
Requires strong understanding of state of the art verification techniques including assertion and metricdriven verification methodology UVMbased
Very competent in System Verilog C C System C and/or Verilog
Experience in writing of CPF/UPF to enable multiple power domain verification
Strong experience in working in Synopsys VCS or Cadence IES and other formal verification tools
Verification experience and working knowledge of ARM based CPU Core SPI I2C UART I2C USB PCIe and/or any other wired protocol with transceivers are strong added advantages
Capable of leading review and guiding younger verification engineers in their daily verification tasks
Able to work in a team with a strong drive to excel
Able to work independently on a given assignment and work hard to finish on time
Good written and communication skills
Requires BSc/MSc or PhD in electrical and electronic or Computer engineering Requires 5 years or more of experience in building UVM/OVM/VMM equivalent test suite Requires strong understanding of state of the art verification techniques including assertion and metric-driven verification methodology, UVM-based Very competent in System Verilog, C++ , C , System C and/or Verilog Experience in writing of CPF/UPF to enable multiple power domain verification Strong experience in working in Synopsys VCS or Cadence IES, and other formal verification tools Verification experience and working knowledge of ARM based CPU Core , SPI, I2C, UART, I2C, USB, PCIe , and/or any other wired protocol with transceivers are strong added advantages Capable of leading, review and guiding younger verification engineers in their daily verification tasks Able to work in a team with a strong drive to excel Able to work independently on a given assignment and work hard to finish on time Good written and communication skills
Employment Type
Full Time
Key Skills
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