RTL Design Engineer Security
Posted on :
13-06-2024
Employer Active
1 Vacancy
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Job Description
Minimum qualifications:
- 5 years of experience in designing RTL digital logic using System Verilog for FPGA/Application-Specific Integrated Circuit (ASIC).
- Experience in scripting language such as Perl or Python.
- Experience in area, power and performance optimization.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience.
- Experience in design and development of security blocks or crypto blocks.
Employment Type
Full Time
Company Industry
Department / Functional Area
Key Skills
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