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Our vision is to transform how the world uses information to enrich life for all.
We are a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence inspiring the world to learn communicate and advance faster than ever.
Position Description:
To be part of a highly skilled ASIC Team working on the Latest Technology Nodes
Responsible for Technically Leading & Managing an overall IP/SS Verification from TestPlan creation UVM development to Signoff
Ensure first pass product through multidimensional Verification Coverage
Mentoring and Coaching Team Members
Stakeholder Management & Mitigation Planning ensuring key Milestones Schedule/Quality
Pair with similar Domain Specialists across other Geographical locations on Core Technical Initiatives
SKILLS required:
Good knowledge of Memory Controller & PHY LPDDR5/DDR4/5 Protocols
Good understanding of NOC Designs AMBA Protocol(s) and RAS Techniques
Strong Leadership skills and ability to Hire & Mentor Team Members
Proven track record of building Testplan UVM Environment from Scratch
Experience with RTL Debugging ScoreBoard/Assertion Development and Code Coverage Analysis
Sound knowledge of System Verilog and UVM Methodology
The position requires good Written & Verbal Communication Skills
Strong Commitment and ability to work in Cross Functional & Globally Dispersed Teams
M.S./M.Tech BS/BE (Electronics)
Experience Required : 10 Years
Full Time