RTL Design and Verification Engineer
RTL Design and Verification Engineer
Posted on :
10-03-2024
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Job Description
RTL Design and Verification Engineer
Location: Hybrid to Austin TX
Duration: 6 months extendable
Hybrid Austin TX (Required to work onsite every Wednesday)
MF; 9am 6pm CST
RTL Design and Verification
You will be involved in deep submicron IC logic and VLSI design validation development developing verifying and validating competitive solutions with Clients PROM circuit technology for use in mobile IOT client network and server segments. Job responsibilities include RTL design and validation for Fuse Soft IP developing tests for designs and validating PROM Subsystem IP and Controller designs identifying potential design limitations and bugs that can impact design margin and component yield. Provides PostSi support including but not limited to characterization test definition debugging product returns as well as reviewing and dispositioning results.
Behavior traits:
Clear documentation and communication skills: thorough concise effective documentation of logic design verification and testing is expected as well as IP integration support to SoC customers timely communication and careful consideration of customer requests.
MUSTHAVE Qualifications:
Bachelors degree in electrical engineering with 3 experience or masters degree in electrical engineering or related field with 2 year experience.
Experience in Logic design validation and testing including but not limited to:
Microarchitecture definition of design features test plan creation and functional verification.
Effective behavioral modeling and testing of circuits in Verilog and System Verilog as well as logical equivalence verification between Schematic and Verilog models.
UPF (Unified Power Format) creation using low power techniques and handling multiple power domain design.
Knowledge of Clock Domain Crossing Design for Test Register Description Language.
Experience in test bench creation to generate test patterns and vectors.
GoodtoHave qualifications:
Solid understanding of state machines and industrystandard protocols such as JTAG
Knowledge of UVM and OVM verification.
Experience in PreSi validation creation of test plan test bench & test case development review and debug of test results and coding assertions to prevent illegal states.
Experience in PostSi characterization and debug including proposing and writing tests and experiments and reviewing results.
Experience in product development and testing using industrystandard tools.
Experience in scripting languages (perl tcl etc.) to enhance automation in design validation and testing is recommended.
MF; 9am 6pm CST
RTL Design and Verification
You will be involved in deep submicron IC logic and VLSI design validation development developing verifying and validating competitive solutions with Clients PROM circuit technology for use in mobile IOT client network and server segments. Job responsibilities include RTL design and validation for Fuse Soft IP developing tests for designs and validating PROM Subsystem IP and Controller designs identifying potential design limitations and bugs that can impact design margin and component yield. Provides PostSi support including but not limited to characterization test definition debugging product returns as well as reviewing and dispositioning results.
Behavior traits:
Clear documentation and communication skills: thorough concise effective documentation of logic design verification and testing is expected as well as IP integration support to SoC customers timely communication and careful consideration of customer requests.
MUSTHAVE Qualifications:
Bachelors degree in electrical engineering with 3 experience or masters degree in electrical engineering or related field with 2 year experience.
Experience in Logic design validation and testing including but not limited to:
Microarchitecture definition of design features test plan creation and functional verification.
Effective behavioral modeling and testing of circuits in Verilog and System Verilog as well as logical equivalence verification between Schematic and Verilog models.
UPF (Unified Power Format) creation using low power techniques and handling multiple power domain design.
Knowledge of Clock Domain Crossing Design for Test Register Description Language.
Experience in test bench creation to generate test patterns and vectors.
GoodtoHave qualifications:
Solid understanding of state machines and industrystandard protocols such as JTAG
Knowledge of UVM and OVM verification.
Experience in PreSi validation creation of test plan test bench & test case development review and debug of test results and coding assertions to prevent illegal states.
Experience in PostSi characterization and debug including proposing and writing tests and experiments and reviewing results.
Experience in product development and testing using industrystandard tools.
Experience in scripting languages (perl tcl etc.) to enhance automation in design validation and testing is recommended.
Employment Type
Full Time
Key Skills
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