- Looking for an IP/SOC design verification engineer.
- Must have experience in System Verilog and UVM.
- Good to have experience in any protocol like AXI, AMBA, I2C, DDR, PCIe, USB, Ethernet, Multimedia etc.,.
- Should have good debugging and analytical skills.
- Good to have Scripting knowledge (Python/Perl/shell).
- Good communication skills and ability, desire to work as a team player.
Roles and responsibilities:
- Responsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies.
- You are expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
- Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.
- Use advanced verification methodologies like SV/UVM.