Warehouse Environment Jobs in Ho Chi Minh City

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

JOB OBJECTIVETo ensure that the solutions offered are tailored to meet the customers requirements by working closely with sales team.JOB RESPONSIBILITIES Works closely with the sales team on proposals and pitches for business.Attends meetings with Sales Managers and acts as a solution More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

All qualified candidates will be given fair consideration. Per GDPR any CV or personal information you submit will be used strictly for recruitment. Your data will be processed based on legitimate interest securely stored and not shared outside the recruitment process. About The Comp More...

Our team is performing design for system IP (such as CPG SYSC) as the below steps: Make DRBFM target specification implementation specification. Understand clock/reset/power structure for whole SoC to generate/coding full or a part of IP. Understand to create timing constraint for IP More...

Define DFT strategy architecture and provide technical guideline for DFT design & verificationPerform DFT design and verification (MBIST SCAN LBIST...)DFT mode SDC (timing constraint) develop & analysis.Analyze & improve test coverage test time reduce area/timing/routing c More...

Lead shape and facilitate analysis and feasibility work with stakeholders for emerging change initiatives to build the business case for project activityEstablish and maintain professional and consultative relationships with customersAssess the clients business needs and business proc More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

All qualified candidates will be given fair consideration. Per GDPR any CV or personal information you submit will be used strictly for recruitment. Your data will be processed based on legitimate interest securely stored and not shared outside the recruitment process. About The Comp More...

Job description: We are seeking a highly motivated and experienced SoC Design Verification Manager to join our team. In this role you will manage and lead a team to contribute to the verification of complex SystemonChip (SoC) designs ensuring functionality performance and quality More...

Our team guarantee Gate netlist and SDC (Synopsys Design Constraint) qualification for Automotive SoCs. Our responsibility includes : RTL/Netlist qualification: Perform LSI ChipTop netlist check such as VC Spyglass CDC Renesas In House Tool such as FalseCheck for asynchoronus design M More...

Our team guarantee Gate netlist and SDC (Synopsys Design Constraint) qualification for Automotive SoCs. Our responsibility includes : RTL/Netlist qualification: Perform LSI ChipTop netlist check such as VC Spyglass CDC Renesas In House Tool such as FalseCheck for asynchoronus design M More...

Our team guarantee Gate netlist and SDC (Synopsys Design Constraint) qualification for Automotive SoCs. Our responsibility includes : RTL/Netlist qualification: Perform LSI ChipTop netlist check such as VC Spyglass CDC Renesas In House Tool such as FalseCheck for asynchoronus design M More...

Lead shape and facilitate analysis and feasibility work with stakeholders for emerging change initiatives to build the business case for project activityEstablish and maintain professional and consultative relationships with customersAssess the clients business needs and business proc More...

Define DFT strategy architecture and provide technical guideline for DFT design & verificationPerform DFT design and verification (MBIST SCAN LBIST...)DFT mode SDC (timing constraint) develop & analysis.Analyze & improve test coverage test time reduce area/timing/routing c More...