Safe Completion Jobs in Vietnam

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Define DFT strategy architecture and provide technical guideline for DFT design & verificationPerform DFT design and verification (MBIST SCAN LBIST...)DFT mode SDC (timing constraint) develop & analysis.Analyze & improve test coverage test time reduce area/timing/routing c More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Our team is performing design for system IP (such as CPG SYSC) as the below steps: Make DRBFM target specification implementation specification. Understand clock/reset/power structure for whole SoC to generate/coding full or a part of IP. Understand to create timing constraint for IP More...

Define DFT strategy architecture and provide technical guideline for DFT design & verificationPerform DFT design and verification (MBIST SCAN LBIST...)DFT mode SDC (timing constraint) develop & analysis.Analyze & improve test coverage test time reduce area/timing/routing c More...

The Organization The Alliance of Bioversity International and CIAT delivers researchbased solutions that harness agricultural biodiversity and sustainably transform food systems to improve people s lives. Alliance solutions address the global crises of malnutrition climate change bi More...

Define DFT strategy architecture and provide technical guideline for DFT design & verificationPerform DFT design and verification (MBIST SCAN LBIST...)DFT mode SDC (timing constraint) develop & analysis.Analyze & improve test coverage test time reduce area/timing/routing c More...

Define DFT strategy architecture and provide technical guideline for DFT design & verificationPerform DFT design and verification (MBIST SCAN LBIST...)DFT mode SDC (timing constraint) develop & analysis.Analyze & improve test coverage test time reduce area/timing/routing c More...

Define DFT strategy architecture and provide technical guideline for DFT design & verificationPerform DFT design and verification (MBIST SCAN LBIST...)DFT mode SDC (timing constraint) develop & analysis.Analyze & improve test coverage test time reduce area/timing/routing c More...

If you are handson and highlyadaptable persons so you may a person that we are looking for. WHAT YOU WILL DO Establish Quality System guidelines / procedures and supervise the implementation to maintain product quality. From input to end product including SOP for best practices in all More...

Job description: We are seeking a highly motivated and experienced SoC Design Verification Manager to join our team. In this role you will manage and lead a team to contribute to the verification of complex SystemonChip (SoC) designs ensuring functionality performance and quality More...

Our team guarantee Gate netlist and SDC (Synopsys Design Constraint) qualification for Automotive SoCs. Our responsibility includes : RTL/Netlist qualification: Perform LSI ChipTop netlist check such as VC Spyglass CDC Renesas In House Tool such as FalseCheck for asynchoronus design M More...

Our team guarantee Gate netlist and SDC (Synopsys Design Constraint) qualification for Automotive SoCs. Our responsibility includes : RTL/Netlist qualification: Perform LSI ChipTop netlist check such as VC Spyglass CDC Renesas In House Tool such as FalseCheck for asynchoronus design M More...

Our team guarantee Gate netlist and SDC (Synopsys Design Constraint) qualification for Automotive SoCs. Our responsibility includes : RTL/Netlist qualification: Perform LSI ChipTop netlist check such as VC Spyglass CDC Renesas In House Tool such as FalseCheck for asynchoronus design M More...

Job description: We are seeking a highly motivated and experienced SoC Design Verification Manager to join our team. In this role you will manage and lead a team to contribute to the verification of complex SystemonChip (SoC) designs ensuring functionality performance and quality More...

Our team guarantee Gate netlist and SDC (Synopsys Design Constraint) qualification for Automotive SoCs. Our responsibility includes : RTL/Netlist qualification: Perform LSI ChipTop netlist check such as VC Spyglass CDC Renesas In House Tool such as FalseCheck for asynchoronus design M More...