New Graphics Jobs in Ho Chi Minh City

FI subproject manager in SAP S4 implementation projects worldwideDefinition and implementation of new accounting concepts while taking into account of new or changed legal requirements.Initialization and implementation of process adjustments standardization and optimization.Interface More...

Renesas Electronics is looking for a System Analyst to join our IT team supporting our HR applications within the business. The role will work closely with wider IT and HR colleagues as well as other internal and external stakeholders. You will assess needs gather requirements and sup More...

Deploy Procurement system to new Eurofins CompanyReview and update supplier database & procurement databaseSourcing for standard goods/servicesOther purchasing admin tasks assigned by Purchasing teamQualifications : At least 3year student.  Background in Business Administrat More...

FI subproject manager in SAP S4 implementation projects worldwideDefinition and implementation of new accounting concepts while taking into account of new or changed legal requirements.Initialization and implementation of process adjustments standardization and optimization.Interface More...

FI subproject manager in SAP S4 implementation projects worldwideDefinition and implementation of new accounting concepts while taking into account of new or changed legal requirements.Initialization and implementation of process adjustments standardization and optimization.Interface More...

Your New Roles:Application monitoring to ensure stable and optimal performance always.Have ability to understand and reasonably resolve basic and complex technical problems.Have ability to work under pressure prioritize and manage multiple tasks.Good Teamplayer with strong Interperson More...

Overview of duties: Test products according to SOP or Work Instruction and do other tasks that assigned by direct management.General duties:1. Daily operation:Perform testing products for every test method assigned by direct superior.Ensure reports issue on time and accuracy2. De More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Our team is performing design for system IP (such as CPG SYSC) as the below steps: Make DRBFM target specification implementation specification. Understand clock/reset/power structure for whole SoC to generate/coding full or a part of IP. Understand to create timing constraint for IP More...

Our team is performing design for system IP (such as CPG SYSC) as the below steps: Make DRBFM target specification implementation specification. Understand clock/reset/power structure for whole SoC to generate/coding full or a part of IP. Understand to create timing constraint for IP More...

Our team is performing design for system IP (such as CPG SYSC) as the below steps: Make DRBFM target specification implementation specification. Understand clock/reset/power structure for whole SoC to generate/coding full or a part of IP. Understand to create timing constraint for IP More...

Define DFT strategy architecture and provide technical guideline for DFT design & verificationPerform DFT design and verification (MBIST SCAN LBIST...)DFT mode SDC (timing constraint) develop & analysis.Analyze & improve test coverage test time reduce area/timing/routing c More...

ACG2088JOBOur client is a leading bank in Vietnam who is looking for a qualified candidate to join their firm:Overall manage Retail Banking business operations to achieve goals and implement initiatives that contribute to the implementation of business strategies within the legal and More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Work with client and team closely participate in team activities or eventsPerform all testing activities independently and effectively: test estimation test planning test strategy test cases design test execution defects tracking etc.Understand automation frameworks can maintain More...