Design Solution Jobs in Vietnam

Our team guarantee Gate netlist and SDC (Synopsys Design Constraint) qualification for Automotive SoCs. Our responsibility includes : RTL/Netlist qualification: Perform LSI ChipTop netlist check such as VC Spyglass CDC Renesas In House Tool such as FalseCheck for asynchoronus design M More...

Our team guarantee Gate netlist and SDC (Synopsys Design Constraint) qualification for Automotive SoCs. Our responsibility includes : RTL/Netlist qualification: Perform LSI ChipTop netlist check such as VC Spyglass CDC Renesas In House Tool such as FalseCheck for asynchoronus design M More...

Our team guarantee Gate netlist and SDC (Synopsys Design Constraint) qualification for Automotive SoCs. Our responsibility includes : RTL/Netlist qualification: Perform LSI ChipTop netlist check such as VC Spyglass CDC Renesas In House Tool such as FalseCheck for asynchoronus design M More...

Our team guarantee Gate netlist and SDC (Synopsys Design Constraint) qualification for Automotive SoCs. Our responsibility includes : RTL/Netlist qualification: Perform LSI ChipTop netlist check such as VC Spyglass CDC Renesas In House Tool such as FalseCheck for asynchoronus design M More...

Job description:We are seeking a highly motivated and experienced Senior SoC Design Verification Engineer to join our team. In this role you will lead and contribute to the verification of complex SystemonChip (SoC) designs ensuring functionality performance and quality meet project a More...

ACG2436JOBOur client a fast growing company specialized in the real estate industry is looking for a qualified candidate to join their firm. In this role the person in charge is expected to take responsibilities for 3 task groups: Responsible for all designrelated work; Recruit manage More...

ACG2434JOBOur client a fast growing company specialized in the real estate industry is looking for a qualified candidate to join their firm. In this role the person in charge is expected to take responsibilities for 3 task groups: Responsible for all designrelated work of the departme More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Your Responsibilities: Analyze project requirements and determine the most effective technical solutions.Design develop and maintain highperformance reusable and reliable code.Collaborate on solution architecture component design and the technical development of key project functional More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Static timing analysis and timing closure (TOP and block). Propose technical solution to enhance the design from RTL to GDS to achieve timing closure. Collaborate with FE/BE teams to finish chip design within definited schedule.Qualifications : Bachelor or Master Degree in Informat More...

Lead technical of the team to make technical decision in terms of the architecture and technology choices for the applicationsEnsure code quality and development practices are followed code written by you and your team adheres to standards for accessibility scalability usability secur More...