Verification Engineer Soc Jobs in Doha

Conduct design verification using SystemVerilog/UVM, C/C++. Develop an integration test environment using VIP (Verification IP). Create checkers and scoreboards for verification. Verify the design using SystemVerilog ertions. Develop a comprehensive test plan for verification ta More...

Preferred qualifications: Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) and/or ASICs. Experience creating and using verification components and environments in standard verification methodology. Exper More...