ASIC Design Engineer -Axiado
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Job Description
Position:ASIC/SOC Design Engineer
Location:Hyderabad
Exp:5 Yrs to 20 Yrs
Job Description:
ASIC/SoC Design position is your opportunity to join one of the industry s leading companies in Smart Edge SoCs for network/systems control management security systems and IIoT. You should have prior knowledge of logic design and computer architecture. As the ASIC/SoC Design Engineer for Axiado you will have the opportunity to work in all areas of the SoC design flow. You will work closely with the Architecture Verification Physical Design and Software teams and report to the Director of Engineering.
KEY RESPONSIBILITIES
- Help develop the design and implementation of SoCs.
- Microarchitecture design RTL coding synthesis timing closure and documentation of various RTL blocks;
- Toplevel and blocklevel performance bandwidth and power optimization;
- Work with FPGA engineers to perform early prototyping; and
- Support test program development chip validation and chip life until production maturity.
- Collaboration with firmware software DV FPGA DFT SoC integration and backend teams throughout various stages of ASIC development.
Qualifications
- 8 years of experience in RTL logic design verification synthesis and timing optimization;
- Proficient in writing clear implementable microarchitecture specifications;
- Expertise in writing efficient RTL code in Verilog and SoC integration
- Good understanding of assertions coverage analysis RTL synthesis and timing closure;
- Should have worked on interface protocols like PCIe USB Ethernet DDR3/4 LPDDR I2C/I3C SPI SD/SDIO/eMMC UART etc.
- Experience in design bring up and debug on FPGA based emulation platforms like HAPS Veloce.
- Fluency with scripting languages (e.g. Perl Python);
- Must have gone through at least one tapeout.
- Preferred: Silicon bringup and debug experience
- Experience in working with repository management tools like Bitbucket/ Jenkins and bug tracking tools like JIRA.
verification,synthesis,asic design,repository management (bitbucket/jenkins),integration,rtl coding,scripting languages (perl, python),design,timing optimization,soc,fpga based emulation,micro-architecture specifications,soc integration,verilog,bug tracking (jira),interface protocols (pcie, usb, ethernet, ddr3/4, lpddr, i2c/i3c, spi, sd/sdio/emmc, uart),rtl logic design
Employment Type
Full Time
Key Skills
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