Post Silicon Validation Engineer Ethernet
Post Silicon Validation Engineer Ethernet
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Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
Location: Santa Clara CA (Onsite)
Analyze and debug test failures independently to identify root cause.
Debug complex crossfunctional issues with ASIC system hardware and software engineers.
Build powerful programs in Python and C to automate testing regression and debugging.
5 years of relevant postsilicon validation experience.
Proficiency with lab equipment logic analyzers and oscilloscopes.
Expertise in Python and C.
Thorough understanding of Ethernet PHY / PCS / MAC standards (e.g. IEEE 802.3) and technologies.
Proven success in functional and electrical bringup and validation of PAM4 and NRZ Ethernet interfaces on multiple ASICs.
Handson experience with traffic generators such as Spirent and Ixia
Demonstrated ownership and independence in planning analyzing debugging driving vendors and reporting status.
Strong collaboration and communication skills.
Education:
BS or MS in EE CE or CS or equivalent experience.
Required Skills:
OSCILLOSCOPES
ETHERNET
VALIDATION ENGINEER
PYTHON
LOGIC ANALYZERS
Additional Skills:
PCS
ASIC
APPLICATIONSPECIFIC INTEGRATED CIRCUIT
GENERATORS
ASICS
IEEE
DEBUG
MAC
Employment Type
Full Time
