Memory FW Engineer - Senior US
Memory FW Engineer - Senior US
Posted on :
10-12-2024
Employer Active
1 Vacancy
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Monthly Salary
Not Disclosed
Salary Not Disclosed
Vacancy
1 Vacancy
Posted on :
10-12-2024
Job Description
Title: Memory Firmware Engineer
Location: Boxborough MA (Remote is Ok)
Duration: 12 minths contract
The Person:
Will have strong analytical/problemsolving skills and pronounced attention to details. Must be a selfstarter and able to independently drive tasks to completion. Will have strong interpersonal and communication skills
The Role:
The Memory IO team is looking for a passionate and experienced Firmware designers for the pre/postsilicon development of highspeed LPDDR DDR and interchip IO IPs. Be a part of the definition design and development and productization phase of industryleading Memory PHYs and interface IP. This opportunity includes enabling of new PHY designs at the microarchitecture firmware/hardware codesign and algorithm design level.
Be a part of a team that delivers Industry leading IP and help our experts in RTL FW circuit and architecture teams develop leading edge Memory interfaces.
RESPONSIBILITIES:
Firmware design and development of DDR PHY & DRAM Training steps
Firmware development of DDR PHY for ATE Testing IP Char & SoC Power
Presilicon FW coding and simulation against Architectural and RTL models
Postsilicon lab bringup and optimization of DDR Init and Run Time FW
Postsilicon DDR Training enhancements to enable robust links for higher reliability / higher frequency margin
Working with SoC/Product firmware teams to define features and specs
Preference & Skill Sets :
5 years experience as firmware engineer.
Excellent knowledge of C C and any scripting language such as Python.
Good Knowledge of Verilog/SystemVerilog and digital simulation debug.
Ability to adapt learn new toolsets and frameworks is required.
Strong understanding of synchronization techniques (handshakes message passing); knowledge of hardware level clocking and synchronization is a plus
Postsilicon experience developing firmware on real hardware is required. Experience with SERDES DDR Memory Controller Design experience is preferred
Strong understanding of computer organization/architecture.
Laboratory experience including the use of equipment: oscilloscopes logic analyzers etc.
Experience with low level physical phenomenaoriented logic design is an asset (dealing with IO clocking voltage control etc.)
EDUCATION:
Bachelors degree in electrical or computer engineering is strongly desired. Masters or PhD degree is a plus.
Title: Memory Firmware Engineer
Location: Boxborough MA (Remote is Ok)
Location: Boxborough MA (Remote is Ok)
Duration: 12 months contract
The Person:
Will have strong analytical/problemsolving skills and pronounced attention to details. Must be a selfstarter and able to independently drive tasks to completion. Will have strong interpersonal and communication skills
The Role:
The Memory IO team is looking for a passionate and experienced Firmware designers for the pre/postsilicon development of highspeed LPDDR DDR and interchip IO IPs. Be a part of the definition design and development and productization phase of industryleading Memory PHYs and interface IP. This opportunity includes enabling of new PHY designs at the microarchitecture firmware/hardware codesign and algorithm design level.
Be a part of a team that delivers Industry leading IP and help our experts in RTL FW circuit and architecture teams develop leading edge Memory interfaces.
RESPONSIBILITIES:
Firmware design and development of DDR PHY & DRAM Training steps
Firmware development of DDR PHY for ATE Testing IP Char & SoC Power
Presilicon FW coding and simulation against Architectural and RTL models
Postsilicon lab bringup and optimization of DDR Init and Run Time FW
Postsilicon DDR Training enhancements to enable robust links for higher reliability / higher frequency margin
Working with SoC/Product firmware teams to define features and specs
Preference & Skill Sets :
5 years experience as firmware engineer.
Excellent knowledge of C C and any scripting language such as Python.
Good Knowledge of Verilog/SystemVerilog and digital simulation debug.
Ability to adapt learn new toolsets and frameworks is required.
Strong understanding of synchronization techniques (handshakes message passing); knowledge of hardware level clocking and synchronization is a plus
Postsilicon experience developing firmware on real hardware is required. Experience with SERDES DDR Memory Controller Design experience is preferred
Strong understanding of computer organization/architecture.
Laboratory experience including the use of equipment: oscilloscopes logic analyzers etc.
Experience with low level physical phenomenaoriented logic design is an asset (dealing with IO clocking voltage control etc.)
EDUCATION:
Bachelors degree in electrical or computer engineering is strongly desired. Masters or PhD degree is a plus.
Regards
Prachi Sharma
Employment Type
Full Time
Key Skills
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