Design Engineer
Design Engineer
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Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
10 years of design experience in developing synthesis constraint at module and Full Chip level
Experience in promoting subsystem level RDC/CDC constraint to SoC Top
Experience in debugging and triaging Lint CDC/RDC errors or issues
Experience in converting spyglass constraints to realintent constraints
Experience in creating lint RDC/CDC constraints both at IP level Fullchip or Top level
Experience in promoting IP level or SoC Constraints
Employment Type
Full Time
