DFT Engineer
DFT Engineer
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Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
- Work with frontend team DFT and crossfunctional teams to provide the solutions and make sure DFT DRCs are fixed
- Generating highquality manufacturing ATPG test patterns for (SAF) stuckat transition fault (TDF) Path Delay fault (PDF) models and through the use of onchip test compression techniques.
Requirements
- BE/ BTech/ MTech/MS/ PhD in Electronics Electrical Computer Engineering or Computer Science Engineering with 4 10 years of exp.
- Highly motivated and driven to face challenging design and debug problems
- Indepth knowledge and handson experience in scan insertion ATPG coverage analysis and Transition delay test coverage analysis.
- Analyze the design and propose the best compression technique.
- Indepth knowledge and handson experience in Scan insertion and validation BIST LBIST MBIST insertion and verification ATPG IP tests and Pattern Validation w/wo Timing DFT mode timing analysis and signoff.
- Handson experience in various DFT aspects like Scan insertion MBIST and Boundary Scan ATPG Pattern validation at block level as well as Fullchip level
- Tessent DFT expertise methodology and flow development
- Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is desired.
- Scripting Languages Shell scripting Python TCL PERL etc.
- Be able to work and support Test Engineers for postsilicon tasks.
Employment Type
Full Time
