DFT Engineer
Posted on :
23-08-2024
Employer Active
1 Vacancy
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Job Description
Job Responsibilities
- Perform Core and SOC level ATPG to meet Automotive grade quality.
- Hierarchical ATPG retargeting and Pattern release for application on ATE.
- Perform SOC and Core level Timing/Nontiming GLS.
- Silicon brings up diagnoses and provides support for physical failure analysis.
- Enable Emulation of Gate level SCAN patterns
- Silicon brings up diagnoses and provides support for physical failure analysis.
- Enable Emulation of Gate level SCAN patterns
Experience:
1.6 (desirable) years in DFT and test flow with commercial EDA tools for complex SOC.
2. Strong fundamental knowledge of DFT techniques including JTAG ATPG yield learning logic diagnosis Scan compression and IJTAG. and MBIST/LBIST.
3. Experience in Tessentbased ATPG flow GLS and Postsilicondebug.
Handson in Perl/Tcl/Python scripting;
4. Excellent analytical and problemsolving skills
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Employment Type
Full Time
Key Skills
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