ACG2152JOB
Our client is a leading technology company in Vietnam who is looking for a qualified candidate to join their firm:
- Execute the NetlisttoGDS design process which involves floor planning placement timing optimization clock tree synthesis and routing.
- Provide assistance for STA timing analysis and resolution.
- Conduct physical verification which involves doing DRC LVS comparison analyzing IR drop and conducting DFM analysis.
Requirements
- Electrical Engineering/Computer Science.
- At least 3 years of experience.
- Proficient in using Cadence Innovus or Synopsys ICC2/Fusion Compiler.
- TOEIC score between 730 and 855 is desirable.
- Prior expertise in IC design at 65/40/28nm will be advantageous.
Contact: Giang Tran or Nga Dang
Due to the immense number of applicants only shortlisted candidates will be contacted
Electrical Engineering/Computer Science. Proficient in using Cadence Innovus or Synopsys ICC2/Fusion Compiler. TOEIC score between 730 and 855 is desirable. Prior expertise in IC design at 65/40/28nm will be advantageous. Contact: Giang Tran or Nga Dang Due to the immense number of applicants, only shortlisted candidates will be contacted