Senior Physical Design Engineer
Posted on :
04-07-2024
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Monthly Salary
Not Disclosed
Salary Not Disclosed
Posted on :
04-07-2024
Job Description
Job Reference QWY475WW
Job Description
- Perform NetlisttoGDS design flow including floor planning placement timing optimization clock free synthesis and routing
- Support STA timing analysis and fixing
- Perform physical verification including DRC LVS IR drop and DFM analysis
Job Requirement
- Graduated in EE/CS
- From 3 years working experiences
- Toeic 730855 is preferred
- Familiar with Cadence Innovus or Sysnopsys ICC2/Fusion Compiler
- Have experiences in 65/40/28nm IC design experiences will be plus
What we offer
- Competitive salary package
- Free motorbike parking
- Monthly meal & transportation allowances
- Premium healthcare package applies since probation
- Premium healthcare package for family member after probation
- Annual health check company trip voucher/ gifts in birthday & special holidays
- Dynamic environment & talent people
Remote Work :
No
Employment Type
Full Time
Key Skills
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