- Experience working on bulk technology nodes TSCM 65nm 40nm 28nm etc.
- Experience with floor planning matching balancing and DFM issues.
- Experience using Cadence and other tools including lef and PEX netlist generation.
- Experience of LVS Density lower node DRC s Parasitic reduction and LDE challenges.
- Experience in the layout of a wide variety of circuit types is required: i.e. Highspeed circuits ESD Amplifiers Drivers PLLs Bandgap Equalizer CDR Serdes LDOs PLLs etc.
- Experience working on bulk technology nodes TSCM 65nm 40nm 28nm etc.
- Experience with floor planning matching balancing and DFM issues.
- The position also requires knowledge of common circuit layout practices such as: matching techniques ESD/Latchup mitigation techniques Antenna LDE EMIR and circuit parasitic reduction etc.
- 68 years of Analog Layout Design experience
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