SoC Debug and interconnect Design LeadMethodology
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Job Description
Debug and interconnect Design Lead/Methodology
Job Summary
SoC Debug is very crucial in chip design as it helps identify and resolve issues that can arise during the development and post silicon testing. Effective and consistent SoC Debug infrastructure ensures the functionality performance and reliability of the chip. It helps in pinpointing and fixing errors optimizing power consumption and enhancing overall system integration. SoC debug plays a vital role in delivering highquality reliable SoCs to our customers in reducing the time to market.
This position will require
Key Challenges:
Job Qualifications:
BTech/MTech/Ph.D. in Electrical/Computer Engineering or other similar disciplines with at least 8 years of relevant experience.
- Understand interconnect protocols like AHB/AXI/ACE/ACELite/NoC concepts.
- Good knowledge of Digital Design and RTL development Handson experience with SoC Design Verilog RTL coding
- Understanding of multicore ARMv8/v9 CPU architecture coherency protocols and virtualization
- Working knowledge of Synthesis DFT verification and silicon debug.
- Working knowledge of Lint CDC PLDRC CLP etc
- Basic Knowledge of System Architecture
- Familiarly with system design SOC microarchitecture and/or design
Job locations: Bengaluru
We are 26 years old company catering to top notch companies catering to Semicon Industries Telecom and System Software. We are operating out of Delhi Bengaluru and Hyderabad.
Employment Type
Full Time
