Technical Specialist
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Job Description
Role: Technical Specialist
Location:Remote
Duration: Long Term Contract
Statement of Work:
Be part of a dynamic and skilled IBM research team developing and implementing an accelerator solution for deep learning workloads based on the use of advanced agile RTL/FPGA generation (and optimization). The design will consist of the RISCV cores DNN accelerator memory block IO blocks and Fully Homomorphic Encryption (FHE) engine. The scope will cover individual tile logic design place and route and functional verification to ensure a working chip for a defined set of workloads. These design blocks will be integrated via ESP design methodology. ESP is an opensource research platform for heterogeneous systemonchip design that combines a scalable tilebased architecture and a flexible systemlevel design methodology developed at Columbia University. ESP provides three accelerator flows: RTL highlevel synthesis (HLS) machine learning frameworks. All three design flows converge to the ESP automated SoC integration flow that generates the necessary hardware and software interfaces to rapidly enable fullsystem prototyping on FPGA. The candidate will extend the ESP capabilities to integrate newly developed tile blocks (such as FHE blocks) and implemented the accelerator SoC design using the enhanced ESP methodology.
Task Description:
Required skills/Level of Experience :
1) Strong experience in architecture level design space exploration for performance and power optimization.
2) Proficiency in at least one hardware description language: Verilog SystemVerilog VHDL and cadence digital implementation tools: Genus/Innovous
3) Simulation skills for full chip verification required (creating test bench design partitioning etc.)
4) FPGA implementation and emulation methodology
5) Ability to debug errors and solve problems in a team environment independently but not in isolation.
6) Familiarity with ESP design methodology opensource research platform for heterogeneous systemonchip design that combines a scalable tilebased architecture and a flexible systemlevel design methodology
7) Fluent English (both verbal and written) and strong communication and presentation skills.
Nice to have skills:
- Preferred: Experience with architecture level design space exploration.
- Preferred: RTL coding and FPGA implementation using commercial tools
- Preferred: FPGAbased emulation experience using commercial tools
- Preferred: Experience with advanced submicron semiconductor technology nodes (sub 10nm)
Employment Type
Full Time
