Asic RTL Design Engineer

AndGate Informatics Pvt. Ltd. is a technology solutions and recruitment company based in Bengaluru. Founded by industry professionals with extensive experience in Semiconductor IT/Software and Recruitment & Staffing AndGate Informatics serves clients in India Malaysia Singapore Vietnam Taiwan US and UK. With a global team we specialize in domains such as ASIC Design and Verification Design for Testability Physical Design and Verification Analog and Mixed Signal Engineering FPGA Design and Verification Embedded and IoT Database Engineering and Artificial Intelligence and Machine Learning.

Requirements

Expertise in SoC/IP design.
Expertise in IP design Subsystem/Cluster and SoC level integration using Verilog/System Verilog.
In depth knowledge on RTL quality checks (Lint CDC).
Knowledge of synthesis and low power is a plus.
Good understanding of AMBA bus protocols (AXI AHB ATB APB).
Good understanding of timing concepts.
Knowledge of one or more of the interface protocols like PCIe DDR Ethernet I2C UART SPI.
Expertise in setting up and using tools like Spyglass Lint/CDC Synopsys DC Verdi/Xcellium
Understanding of scripting languages like Make flow Perl shell python etc.
Understanding of processor architecture and/or ARM debug architecture is a plus.
Able to help and debug issues for multiple subsystems.
Able to create/review design documents for multiple subsystems.
Able to support physical design verification DFT and SW teams on design queries and reviews. 
Bachelors degree in electrical engineering Computer Engineering or related field
3 to 10 years of experience as Asic RTL Design Engineer