Job Responsibilities:
- Be the subject expert for systemonchip (SoC) internal architectures to maximize ECU hardware design efficiency/performance in ADAS and Infotainment applications
- Work proactively with silicon vendor partners to drive future features and solutions
- Be the reference for the SoC IP blocks and design tradeoffs: ARM RISCV GPU DSP ISP NPU MMA HW accelerators
- Be the reference for the bestinclass ISO26262 and Cyber Security implementations
- Support HW Engineering group during advanced design phases system architecture definitions and ECU development / Qualifications
- Be the interface within the organization between the HW Engineering and the Semiconductor groups for high level SoC specifications
- Drive internal SoC roadmap definitions by regularly providing survey study of the relevant industry technologies and SoC solutions
- Be the reference for FPGA definition and usages
Basic Qualifications
- Experience in Silicon SoC Design for embedded electronics or mixed experience of design SoC architecture and TIER2 AE/FAE role
- Experience in EE architecture topologies software architecture Functional safety
- Track record of firstpass success in ASIC development
- Strong teamwork spirit; excellent oral and written communication skills; ability to work independently within a global team environment
- Experience with Silicon Design suite tools
- Familiar with industry standards for chip design methodologies and verification
Preferred Qualifications
- Experienced in industrial or automotive (preferred) market
- Justified experience in ARM 32/64bits architecture power management high speed communication interfaces memories video and audio interfaces
- Justified experience in HW segregation Neural Networks hypervisor technologies
- Experience in defining microarchitecture specifications
- Familiar with 3rd party IPs and SoC integration
- Experience with RISCV and Chiplet technology is a plus
- Solid understanding of embedded electronics design constraints at the component and system level
system on chip,risc-v,hw engineering,arm 32/64bits architecture,infotainment applications,power management,dsp,adas,ee architecture topologies,soc specifications,isp,oral and written communication skills,gpu,3rd party ips,arm,npu,video and audio interfaces,risc-v and chiplet technology,memories,hypervisor technologies,hw segregation,soc integration,ecu hardware design,industrial,iso26262,high speed communication interfaces,embedded electronics,tier2 ae/fae,embedded electronics design,system-on-chip (soc),teamwork spirit,neural networks,micro-architecture specifications,software architecture,automotive,design,mma,silicon design suite tools,silicon soc design,soc,cyber security,verification,functional safety,soc ip blocks,chip design methodologies,global team environment,asic development,silicon vendor partners,hw accelerators,semiconductor,soc architecture,fpga