Founded in 2019 by Philippe Notton and financed by the European Union SiPearl embodies Europes dream of mastering the technological heart of its supercomputers: the microprocessor.
Since our creation in 2019 we host 170 collaborators in 6 offices: France (MaisonsLaffitte Massy Grenoble Sophia Antipolis) Germany (Duisburg) Spain (Barcelona).
After a successful series A in 2023 (90M ) SiPearl has recently won an emblematic contract to equip Europes first exascale supercomputer JUPITER who will be operated by the EuroHPCs center of research from Jlich (Germany). And as the dream of a European machine crossing the 1 billion billion mark calculations per second thanks to an European microprocessor is becoming reality SiPearl is willing to hire 150 engineers by the end of 2024!
What a regular day at the job might look like:
Prediction of faultmodels estimation of yield and creation of innovative DfT strategies
Work with the system architecture team to implement the DfT concept
Generate ATE structural and functional testpattern by use of RTL strobing and GatelevelResimulation
Predict and optimize ATE testtime
Identify generate and integrate the DfT IPs needed on RTL and Netlist level
Perform functional verification of DfT structures in RTL level
Perform testspecific verification and coverage analysis of DfT structures in RTL level and Netlist level
Work with IP design teams locally or remotely
Work with verification teams locally or remotely
Work with ASIC service company for chip implementation in different timezones
What would make you succeed in this role:
Graduate from an engineer school or from a Master (5 years diploma post baccalaurat)
A first accomplished experience of 1 year minimum preferably in the micro electronics sector.
Drawn to this type of function in high added value tech sectors.
At least 10 years knowledge in DfT concept and implementation on RTL and/or Netlist level
At least 10 years knowledge in ScanInsertion (all types) MBIST IJTAG BoundaryScan
At least 5 years of knowledge working towards ATE team
Experience in aligning with productionfab understanding their yield parameters
Experience in splitlot and shmoo analysis and failure detection in silicon
Experience in RTL simulation/verification and associated environment
Experience in interaction with constraint development for logical synthesis
Experience in most of the tools: RTL compiler Testkompress/Tetramax Virage/Mentor memory Bist Mentor Bscan Mentor SSN Formal Equivalence tools Ncsim/questasim revision control (git..)
Gained some exposure to digital ASIC front and backend design & verification processes
Good scripting skills e.g. using TCL/Perl/Phyton
Good problemsolving capability
Communicate efficiently across teams
Good sense of independence and patient to learn and search technical information
Good sense of flexibility and adaptation capability/sense of initiative
Ability to document and train others on work developed
Excellent oral and writing English communication
autonomous and flexible
teambuilding mindset
Recruitment process
Discovery interview with our Talent Acquisition Partner (30)
Personality test no need to worry there is no wrong or right answer; our goal is to get to see beyond your resume (45)
Technical interview (1h)
Interview with your future manager (1h)
Benefits and conditions:
Contract:CDI
Benefits: meal vouchers (Sodexo) health insurance (70% covered by SiPearl) 8 to 9 RTTs 5 days per year of remote work from any EU location
Work model: OnSite/Hybrid (2 days remote)
Location: Grenoble Barcelona MaisonsLaffitte Massy Duisburg Valbonne Sophia Antipolis
Awesome activities such as: Hackathons Training Challenges Quarterly Kickoff sessions team events Company events and much more
Are you curious to learn more about us
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At SiPearl we are dedicated to building a diverse and inclusive workplace that thrives on the strength of varied perspectives and backgrounds. We recruit talent based on merit experience and alignment with our companys goals and values.
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