Position Name:Senior Verification Engineer
Description:
Working as a Senior/Principal Mixed Signal Verification Engineer based in Tokyo, you will:
- Be responsible for complete system level (analog + digital + external components) verification.
- Implement simulation test benches/tests that verify the product’s usage scenarios.
- Communicate with analog and digital designers to resolve issues found during verification.
Qualifications:
- Engineering Degree or above in Electronics or equivalent education.
- 3 - 7+ years of experience in Mixed-signal or System level IC verification.
- Experience with Virtuoso.
- Experience with mixed-mode verification. Bench creation, making scenarios, bug reporting, and cooperating with a designer to fix.
- Experience with creating and using real-numbered models in SystemVerilog or analog behavioral models in Verilog-A/MS.
- Familiarity with Linux operation, and scripting languages like Makefile, Perl, Tcl, or Python.
- Experience in UVM-based verification flow is a plus.
- Experience with circuit design is a plus.
- Strong interpersonal, communication, and organizational skills.
- Collaborate with the design team for efficient verification methods.
- Candidates with Management experience will be considered at the Manager level.
- Good English language skills written + oral.
About Company
This company is one of the cores of technological innovation centers and attracts top engineers from all over the world. We have many companies and offices in Japan, offering various engineering and corporate roles.Our mission is to makelives easier and a world that's safer, healthier, greener, and smarter.