Senior Engineer II-Implementation (Design Implementation Engineer)

Design Implementation Engineer

The AES Implementation team is responsible for creating the design of a device by providing technical expertise through cutting edge design tools and technology. This team works closely with various business unit product development teams to ensure the design is physically realizable.

As a Design Implementation engineer, the candidate will be mentored by the team, be engaged into projects to perform the synthesis, DFT implementation, timing closure and ensure the design is implemented correctly with various checks/verification/audit. Also, be involved in design flow/methodology definition and development to ensure the design team is always using best-in-class design methodology.

Responsibilities:

• Perform synthesize, implement Design-For-Test (DFT) and close timing on complex digital integrated circuits at the block, subsystem or device level (100K to 10M+ gates) which are coded in VHDL/Verilog.

• Work with project leaders to meet timing closure, area, power, and performance requirements for macro/device under development.

Requirements

Qualifications:

• Good Knowledge on physical aware synthesis, advance synthesis for power and area optimization, Vector synthesis.
  
• Good Understand Design-For-Test concepts and methodologies (Scan chains, ATPG, BIST, Fault models, Fault Coverage, and generation).
  
• Develop Constraints, analysis and debugging for Func, BIST and DFT modes
  
• Full chip and block level timing closure for various stages of the entire design process (RTL, Synthesis, Place and Route andSTASignoff).
  
• Enhance and maintain allSTAflows and methodology for multiple designs and across different technologies.
  
• Work on all aspects of timing closure including Design rule checks, constraint validation, Noise analysis etc.
  
• Work with various IP owners in developing and refiningSTAconstraints for both full chip and block level.
  
• Low power flow/CPFand conformal low power debug.
  
• Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure
  
• Good in low power techniques and Conformal Low Power
  
• Developing CPF/UPF files
  
• Running Logical Equivalence Check and resolving the issues
  
• Scripting skills in any programming language (preferably Perl, TCL and Shell)
  
• Ability in debugging, problem solving and analytical skills.
  
• Good communication skills
  

Experience:

• Bachelors/Masters in Electronics or equivalent degree with 6+ years of experience
  

Qualifications: Good Knowledge on physical aware synthesis, advance synthesis for power and area optimization, Vector synthesis. Good Understand Design-For-Test concepts and methodologies (Scan chains, ATPG, BIST, Fault models, Fault Coverage, and generation). Develop Constraints, analysis and debugging for Func, BIST and DFT modes Full chip and block level timing closure for various stages of the entire design process (RTL, Synthesis, Place and Route and STA Signoff). Enhance and maintain all STA flows and methodology for multiple designs and across different technologies. Work on all aspects of timing closure including Design rule checks, constraint validation, Noise analysis etc. Work with various IP owners in developing and refining STA constraints for both full chip and block level. Low power flow/CPF and conformal low power debug. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure Good in low power techniques and Conformal Low Power Developing CPF/UPF files Running Logical Equivalence Check and resolving the issues Scripting skills in any programming language (preferably Perl, TCL and Shell) Ability in debugging, problem solving and analytical skills. Good communication skills Experience: Bachelors/Masters in Electronics or equivalent degree with 6+ years of experience