(Electronics) Staff Physical Design Engineer

Unique opportunity to join an established international company in their North America expansion. Working from the NA headquarters, you will have the ability to be an impact player working with some other exceptionally talented people. The Physical Design Engineer will be responsible for the entire product design lifecycle. Top level and block level experience is required. This is a hands-on technical position and will have opportunities to work on a variety of challenging designs. The Staff Physical Design Engineer will work closely with customer, frontend and integration teams to ensure successful tape outs.

Primary Responsibilities:

• Active participation in technical and schedule discussions with ASIC customers and design teams
  
• Chip/Block Level Floorplanning and pin assignment
  
• Pre-layout STA to ascertain feasibility, timing constraint validation and feedback to customers and design teams
  
• Review top-level/block-level clock specifications for completeness and feasibility
  
• Handle all the Physical design tasks (Placement, Timing Optimization, Clock Tree Synthesis, Routing)
  
• Perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis and Physical Verification)
  

Requirements

• BSEE, with 8+ years of experience. MSEE preferred.
  
• Strong experience in ASIC Physical Design; Experience in an SoC product development organization with tapeouts at 28nm/16nm design nodes
  
• Hands-on Experience with implementation EDA tools like ICC2/Innovus
  
• Experience in both Flat and Hierarchical layouts.
  
• Strong problem solving skills and ability to analyze and resolve physical design issues related to library, timing constraints or CAD tools is required.
  
• Experience with power analysis and IR-drop tools (primepower/Redhawk) and Static Timing Analysis (Primetime)
  
• Experience with Physical Verification and fix PV errors in layout
  
• Expert handling of Verilog HDL based Netlists, Physical design libraries, Scripting (Perl/Tcl/Python) is required
  
• Good understanding of ASIC frontend design.
  
• International or Japanese experience a plus