FPGA Verification Engineer ( Chandler, AZ ) 9005

Pay rate: $80-100/hr W2

US Citizenship required

On-site with Hybrid possibility. 50% onsite / 50% offsite

FPGA Verification Engineer with Emphasis on VHDL Verification and Validation.

FPGA verification engineer with at least 5 years of VHDL verification and validation experience to verify VHDL logic for use in aerospace avionics applications.
Requires BSEE with at least 5 years of related work experience or MSEE with at least 3 years of related work experience
Must have proven records of VHDL design verification and validation.
Knowledge of formal verification techniques for VHDL is required.
Must work well on a small team of VHDL design and verification engineers
Must understand the concept of constrained random verification and functional coverage
Be able to write Bus Functional Models BFMs in VHDL
Must be capable of understanding and adhering to department design and verification standards.
Must be familiar with lab testing including lab measurements (oscilloscope, digital logic analyzer), defining test setups, in-circuit debugging.
Familiarity with AMBA AXI and APB is highly desirable.
Familiarity with space fiber and/or space wire is highly desirable.
Familiarity with agile project format is highly desirable.
VHDL design experience is highly desirable

Familiarity with OSVVM ( Open Source VHDL Verification Methodology ) is desirable but will consider candidates with strong VHDL design experience.

Candidate does not have to have both VHDL and Verification Engineer on their resume, it can be one or the other.
On-site with Hybrid possibility.