وظائف في مهندس التحقق من التصميم في الدوحة

Conduct design verification using SystemVerilog/UVM, C/C++. Develop an integration test environment using VIP (Verification IP). Create checkers and scoreboards for verification. Verify the design using SystemVerilog ertions. Develop a comprehensive test plan for verification ta المزيد...

Preferred qualifications: Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) and/or ASICs. Experience creating and using verification components and environments in standard verification methodology. Exper المزيد...

Preferred qualifications: Experience with UVM, SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.. Experience scripting using Python, Perl, or shell scripts. Experience leading and managing complex verification projects. Understanding of ARM ins المزيد...