- Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
- Experience with digital design using SystemVerilog RTL.
Preferred qualifications:
- 4 years of experience with post-graduate digital design using SystemVerilog RTL.
- Experience interacting with software, architecture, and other cross-functional teams.
- Experience applying computer architecture principles to solve open-ended problems.
- Knowledge of processor design, accelerators, or memory hierarchies.