FPGA Design Engineer-VHDL

We are looking for FPGA Design Engineer (VHDL) with 6 to 9 Yrs of Experience for our esteemed client for Bangalore Location.

Key Skills: FPGA VHDL CDC linting synthesis

Note: Minimum Experience is 6 Years. Kindly do not apply if you don t meet the minimum experience.

This is an immediate requirement. Please apply if you can join within 30 days or close to 30 days.

. Strong skills on synthesis CDC and linting.

. Exposure or basic knowledge on system Verilog to align with the verification team for troubleshooting the issues.

1. Resume size shall be less than 300 KB (word document Preferred)

2. Please include Photo In the resume

3. Please include the below details in the resume

First name

Last name

Date of Birth

Fathers Name

last 4 Digits of PAN Number

You will be working with a trusted global product engineering and lifecycle services partner to the world s most recognized companies in the Aero Engines Aerospace & Defense HiTech Transportation (Auto and Rail) Power and Industrial Oil & Gas and Medical Devices industries. With 12K experts and a global presence in 73 locations across 15 countries it believes that it is at the forefront of the convergence of mechanical electronics software and digital engineering innovations to enable solutions for a safer cleaner world. A Strong Process based organization Certified for CMMI L5 and multiple other certifications of the process and one of the few organizations which are ranked as best place to work.