We are now looking for a toplevel verification consultant for our telecom organization.
The work is about partitioning in the toplevel verification of cuttingedge ASICs that power complex highperformance systems. Integrated in multichipmodules are now usually replacing monolithic solutions. Our customer designs hold several hundreds of processor cores DSPs as well as ARM cores and many highspeed interfaces including Ethernet CPRI and PCIe.
Requirements
- Participate in the development of softwaredriven tests written in C.
- Development of sequences for UVM VIPs only required for some of the tests.
- Debug failing test cases using the System C/TLM platform in RTL simulation or the hardware emulator depending on the available platform type of failure and type of test.
- Contribute to keeping your tests clean in the CI regression running on our fourrun platforms.
- Potentially depending on need and interest compilation and partitioning of designs to run in the hardware emulator.
We think that you need at least 5 years of relevant experience to be able to succeed in the role.