Technologist ASIC Development Engineering Design Lead - High-speed IO
Technologist ASIC Development Engineering Design Lead - High-speed IO
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Job Description
Will be part of team responsible for IO and high speed interface solutions for next generation SOCs in advanced CMOS technology nodes.
Will architect IO and high speed interface solutions for SanDisk ASIC controllers.
Will interact with crossfunctional teams to define requirements/specs conceive the optimal solution by evaluating architectures drive implementation closely work with layout designers in guiding and reviewing the layouts ensure timely and highquality deliverables extend SOC integration support and review and provide support for postTapeOut activities such as Silicon characterization .
Provide good technical leadership in problem solving planning and mentoring junior engineers.
Propose innovative design solutions and design methodologies. Help in building a team and developing processes.
Qualifications :
Must have
Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering
Working experience (10 years) in IO including 35 years as project leaders
Should have architected and lead high speed interface design solutions from specification through Silicon debug and characterization
Should have handson experience in TX and RX design architectures for high speed applications such as DDR4/DDR5 along with timing budget analysis.
Should be experienced in high speed design architectures such as SERDES Equalization schemes
Should have handson experience in IPs such as SSTL LVDS I2C POD IOs PVT calibration HV tolerant and Failsafe IOs Crystal oscillator etc
Should have extensive experience in ESD circuits design Associated ESD guidelines and recommendations in different process nodes IO and SOC level ESD review and signoff
Experience in full custom high speed data path design such as DDR PHY will be of advantage.
Conversant with tools such as Cadence Virtuoso/Synopsys custom compiler/Hspice/Spectre/Finesim including statistical simulation methodologies
Experience in Mixedmode simulation and analog/digital cosimulation will be of added advantage.
Experience in creating EDA model such as Verilog model Liberty etc will be of added advantage.
Should have deep understanding and working knowledge of CMOS process including FINFET technologies such as 16nm and the associated DSM issues.
Very analytical in nature and able to work in a multidisciplinary environment
Creative outofthebox thinker with a high level of personal involvement
Strong theoretical background with a pragmatic approach.
Good verbal and written communication skills and experience working with different geographies.
Good mentoring documentation and presentation skills
Additional Information :
Western Digital thrives on the power and potential of diversity. As a global company we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees our company our customers and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging respect and contribution.
Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at to advise us of your accommodation request. In your email please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.
Remote Work :
No
Employment Type :
Fulltime
Employment Type
Full-time
