Interfaces and collaborates with customers to design system
interconnect solutions for AI/ML
Guide architectural system designs analyze compute systems for throughput power latency and cost and create specs for electro
optical transceivers.
Analyze compute systems for throughput power latency and cost
Create specs for electrooptical transceivers guide architectural designs for system interconnects and collaborate with design teams to ensure spec compliance
Work on pathfinding activities and advanced technology and product roadmaps
Experience:
5 to 8 years of experience
Industry experience in physical designs compute systems and network/compute protocols
Experience with HBM and DDR memory subsystems and electrical standards such as UCIe BoW PCIe and Ethernet.
Experience with network protocols and compute software stacks such as RDMA RoCE Ethernet CXL and PCIe
Proficient in programming languages such as C C Python and Shell scripts
Understanding of Ethernet CXL PCIe and NVL switch architecture and fabrics
Participate on SSOs such as OpenCompute UCIe OIF PCISIG UEC UAL CXL and IEEE 802.3
Translate customer key interconnect specifications into protocol requirements to enable silicon photonic interconnects
Participate in technology evangelization through customer presentations conference papers seminar/webinars.
Selfmotivated and detailoriented
Can collaborate and work effectively with colleague across teams and projects
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